The present invention relates generally to integrated circuit memory devices. More particularly, the present invention relates to decoding circuits for memories with redundancy.
Semiconductor integrated circuit memories such as static random access memories (xe2x80x9cSRAMsxe2x80x9d) have used BISR circuits to screen for and sometimes repair certain memory failures in she factory and in the field. BISR circuits typically include a state machine, which is fabricated on the integrated circuit with the memory array for implementing a selected test algorithm. This algorithm is initiated in the factory by an external memory tester. In the field, the algorithm is initiated on start-up.
The prevailing method for detecting faults in SRAMs that have BISR circuits is to screen for these faults in the factory. In the factory, the memory and associated BISR circuit are coupled to a memory tester, which provides a supply voltage and a system clock to the memory array and provides control signals to operate the BISR circuit. Typically, memory testers use a two-pass approach through the BISR circuit test algorithm. In the first pass, memory failures are detected and repaired. In the second pass, the repairs are verified.
A common BISR test algorithm consists of several runs through the memory array. The BISR test algorithm performs a sequence of writes and reads on each cell in the memory array, comparing the output of each read with expected data. When a discrepancy is detected, the BISR test algorithm re-maps the memory addresses to replace the row containing the failing cell with a redundant row. These repairs are verified in the second pass through the BISR test algorithm.
When the memory is installed in the field, the BISR test algorithm is initiated on start-up. Then, during normal operation of the memory array, typical existing systems employ an address matching circuit connected to the input addresses. Incoming addresses are compared against pre-programmed failing addresses on every access cycle. If the incoming address matches a failing address, a redundant memory element is utilized in place of the target memory element. The comparison has a significant timing impact on the system. The more address hits there are, the longer it takes to perform the comparison. Currently, a 10-bit address can take 2 ns (nanoseconds) or more to be matched.
The present invention provides a solution to this and other problems and offers other advantages over the prior art.
The present invention relates to decoding circuits for memories with redundancy.
One embodiment of the present invention is directed to a system for disabling defective memory elements. The system includes a memory array, an address decoder and a decoder element. The memory array has multiple memory elements for storing data. The address decoder receives a requested memory address and produces multiple element-select signals. Each element-select signal is associated with one of the memory elements and indicates whether access to the associated memory element is requested by the host. The decoder element receives one of the element-select signals and provides an output signal to the associated memory element. If the associated memory element is functional, the output signal enables or disables the associated memory element in accordance with the associated element-select signal. Whereas if the associated memory element is defective, the output signal disables the associated memory element regardless of the associated element-select signal.
One embodiment of the present invention further includes a spare memory element and a redundant-address decoder. The spare memory element is able to store data that is intended for a predetermined defective memory element. The redundant-address decoder receives the requested memory address and provides a spare-element-select signal to the spare memory element. The spare-element-select signal enables the spare memory element if the requested memory address matches the address of the defective memory element.
Another embodiment of the present invention is directed to a method of disabling defective memory elements of a memory array Prior to normal operation of the memory array, it is determined whether a particular memory element is functional or defective. An element-select signal indicating whether access to the memory element is requested by a host is received. If the memory element is functional, the memory element is enabled or disabled in accordance with the element-select signal. On the other hand, if the memory element is defective, the memory element is disabled regardless of the element-elect signal.
In a further embodiment of the above method, if the memory element is defective, a spare memory element is provided and the address of the defective memory element is stored. The address of a memory element that the host requests access to is received. The address of the defective memory element is compared to the requested address. If the address of the defective memory element matches the requested address, the spare memory element is enabled.